📂 Load Example
📝 RTL Source Code (Verilog / VHDL)
📄
Click or drag RTL file here
.v, .sv, .vhdl
🔧 Detected Issues (JSON, optional)
📋
Click or drag JSON file
⚙️ Pipeline Stages
1
RTL Parsing (PyVerilog / Regex)2
Bug Detection (4 rules)3
Dependency Graph (NetworkX)4
BFS Impact Analysis5
Feature Extraction6
ML Scoring (Random Forest)7
Hybrid Ranking8
Explanation Generation📊 Dashboard
🔗 Dependency Graph
🧾 Explanations
🤖 ML Insights
🔬
Ready to analyze your RTL design
Paste Verilog / VHDL code on the left and click Analyze RTL🔗
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Run analysis first🧾
No explanations yet
Run analysis firstRandom Forest Feature Importance
Model Configuration
| Algorithm | Random Forest |
| Estimators | 150 |
| Max Depth | 8 |
| Training Samples | 600 (synthetic) |
| Features | 7 |
| Output Classes | Low / Medium / High |
| Training Accuracy | — |
Scoring Formula
rule =
0.40 × reach_output
+ 0.25 × (1/depth)
+ 0.20 × fanout_norm
+ 0.15 × timing_risk
final =
0.70 × rule
+ 0.30 × ml_score
0.40 × reach_output
+ 0.25 × (1/depth)
+ 0.20 × fanout_norm
+ 0.15 × timing_risk
final =
0.70 × rule
+ 0.30 × ml_score